1. Field of the Invention
The present invention relates to electronic packaging and, more particularly, to electronic packaging employing surface mount technology (SMT) wherein passive circuit devices are mounted on the surface of a substrate.
2. Background and Related Art
In the fabrication and assembly of electronic devices on the surface of a substrate, such as a laminate, the process employed typically involves several steps to electrically and mechanically attach the surface mount device (SMD) to the substrate. For example, in the assembly of passive, discrete circuit devices onto a substrate, an adhesive may initially be deposited upon the substrate which adhesive acts to either temporarily or permanently hold the SMD in place. The next step typically involves joining using a solder reflow or dipping process to electrically connect the two terminal SMD to electrical contacts on the substrate. After electrically connecting the SMD to contacts on the substrate, some form of an encapsulant may be used to underfill and/or encapsulate the SMD. Representative of a typical passive device assembly arrangement is that described in U.S. Pat. No. 5,085,364.
One of the difficulties with conventional approaches of this type is that the solder reflow or dipping process typically may leave flux residues in the gap between the SMD and substrate during joining. In addition, further subsequent processing may introduce further contaminants into this gap. Moreover, typical adhesives often do not fully flow into this small gap region. Where the adhesive is cured prior to reflow or dipping, additional contaminants may be introduced during the curing process.
Testing has shown that devices may fail as a result of the above conditions. Failure, at least in part, is due to the fact that the metallurgy of the electrical contact joints can grow dendrites on the surface of the SMD or substrate in the gap region. As a result, the dendrites can electrically short the opposing electrical contacts of the SND causing device failure. Moreover, the flux residues and contaminants introduced as a result of the process employed may also act to produce device failure. In addition, not only does this multi-step process of forming SMDs on the substrate allow introduction of contaminants and voids, it impacts throughput. Each of the steps involves its own process and parameters. As a result, manufacturing cost is higher than desired and, concomitantly, yield is lower than desired.
Commercially available encapsulants, known as noflow or reflow encapsulants, have been employed in the prior art for attaching flip chips and chip scale packages (CSP's) to a substrate. Such encapsulants typically comprise a single component liquid epoxy-based underfill encapsulant containing flux. Flip chip assembly processing demands for higher I/O, combined with variation in gap heights, have prompted the development of encapsulants that enhance solder joint reliability during temperature cycling of flip chips and CSP's. The use of such encapsulants simplifies the assembly process by combining the soldering and underfilling operations.
Such noflow or reflow encapsulants are designed for the assembly and protection of flip chip-type semiconductor devices. They are also typically designed and developed to be compatible with conventional SMT temperature profiles such that they allow for the conventional solder paste assembly processing of SMDs, similar to those described above, concurrently with the noflow or reflow flip chip assembly. The use of the noflow or reflow underfill material eliminates the long underfill times required by standard capillary underfill for flip chips, and is effective in dealing with their wide range of gap sizes.